The present invention relates to solid-state integrated circuits, and more particularly concerns a circuit for sensing the speed of the circuits on a particular chip and the use of performance sensing for stabilizing the performance of circuits on the chip.
The performance characteristics of circuits in a digital integrated circuit vary with unavoidable changes in process parameters during their manufacture, with changes in their supply voltage, and with the temperature of their environment. Even within the same system, it is not uncommon for these "PVT" variations to vary the operating speed and the rate of current change (di/dt) over a very wide range from their nominal values. Logic circuits must therefore be specified for extreme worst-case conditions rather than nearer the nominal values.
Disadvantages accrue at both ends of the performance range. Off-chip driver circuits on a chip increase the power of signals on the chip and supply them to external package pins for transmission to another chip or to some other device. Operation of off-chip drivers greatly in excess of their nominal speed increases their di/dt enough to create excessive spikes on the supply-voltage and ground busses of the chip, which couples enough noise into the logic circuits and signal lines to produce faults in the signals on the chip.
Excessive speed can also cause "early mode" clock failures, resulting in the storing and transmission of false data in the signal lines. Many digital circuits use at least two different clock phases which must be nonoverlapping. For example, a conventional master/slave latch receives and stores the state of its data input at the leading and trailing edges respectively of a first clock pulse, and transmits and stores that data at its output at the rising and falling edges of a second clock pulse. If the clocks overlap, an early-arriving data input level can propagate through the master latch, and then be latched into the slave latch one cycle early.
At the other end of the time scale, a low speed in the chip circuits can cause "late mode" clock failures. In a multi-chip system, each clock line to the various chips are carefully routed on a circuit board or substrate so that the signal arrives at all chips as nearly simultaneously as possible, so that signals traveling from chip to chip can be processed and stored accurately. But PVT variations among the different chips of the system still skew the arrival of the clock signals at the circuits on each chip which process the signals. In conventional chips, this chip-to-chip skew limits the minimum cycle time which can be reliably obtained for the entire system.
Low speed also limits the overall speed of the off-chip drivers. Thus, limiting the di/dt to a safe value for fast circuits may greatly decrease the performance of the entire chip at low circuit speeds.
Of course, tightening the allowable limits of the manufacturing process parameters will reduce the severity of the above problems. Strict temperature control of the environment will also lessen their impact. Tight tolerances on supply voltages, achieved by greater supply regulation and by wider on-chip power-distribution busses, will further reduce the range between worst case and nominal operation, as will lower resistance and inductance of the chip package. Such brute-force solutions, however, are expensive and often conflict with other goals.
Other, less direct, techniques have been employed to reduce the problem of driver noise from excessive di/dt. "Self-Adjusting Stagger Circuit for Drivers," 28 IBM Technical Disclosure Bulletin 2178 (Oct. 1985) forces drivers in different groups to switch at slightly different times, to decrease total chip di/dt. A similar technique is used in "Method for Solving the Delta-I problem in One-Sided Crosspoint Switching Matrices," 28 IBM TDB 2248 (Oct. 1985). "Driver with Noise-Dependent Switching Speed Control," 29 IBM TDB 1243 (Aug. 1986), uses noise feedback to control the effective strength of a pulldown FET. This solution has some advantages, but it is requires special FETs with unusual characteristics, and it relies upon a ground reference that is affected by switching; U.S. Pat. No. 4,437,022 (Miersch, et al.) is similar. U.S. Pat. No. 4,725,747 (Stein, et al.) uses a serpentine polysilicon gate configuration to limit turn-on time; this technique cannot be implemented in some semiconductor technologies, and has other disadvantages as well. U.S. Pat. Nos. 4,398,106 (Davidson, et al.) and 4,508,981 (Dorler, et al.) are not applicable to off-chip drivers, and have diminished value when the chip itself has significant decoupling.
Commonly assigned patent application Ser. No. 110,399, filed on Oct. 20, 1987 for "Method for Digital Slope Control of Output Signals of Power Amplifiers in Semiconductor Circuits" (published by the European Pat. Office on Apr. 27, 1988 under No. 264,470) proposes the broad concept of measuring the performance of the circuits on a chip, and controlling the performance of an off-chip driver circuit in order to stabilize its di/dt within narrower limits over wide PVT variations. However, that compensation circuit depends upon a number of precision components which are expensive, require individual hand adjustment for every system of chips, and/or drift in value over time, temperature and voltage. The driver circuit of this patent requires an additional stage for control purposes, so that its maximum speed is less than drivers having fewer stages. Moreover, that driver has a state in which a signal line is not actively driven to a particular level, but is allowed to float. This allows the output line to be turned on erroneously by noise or undesired coupling to a nearby signal in the circuit. Finally, that patent does not even address the problem of clock skew, either for early-mode or late-mode faults. It thus suggests no way of employing performance sensing to solve those difficulties as well as to alleviate driver problems.
The most common previous solution to variable clock skew is to waste a portion of clock cycle so as to guarantee that the late-mode situation will not occur over the entire expected range of circuit speeds. Early-mode failures can be avoided by padding the circuits between latches with additional inverters. This, however, can use a significant portion of the chip's circuits--as many as 4,000 inverters in a single chip merely for speed compensation alone.